The present invention relates to a large capacity semiconductor memory device.
In semiconductor memory devices, memory cells are generally arranged in a two-dimensional matrix. Memory cells of each row are connected to a row decoder through a corresponding word line. Memory cells of each column are connected to a column decoder through a corresponding bit line. When a row decoder and a column decoder are used to access a single cell in a matrix of memory cells, the decoders are used effectively and a plurality of cells can be accessed.
However, when storage capacity is increased in the above access system, the number of memory cells connected to a single word line and a single bit line is increased, resulting in the following drawback. In general, since the word line is constituted of polycrystalline silicon, it has a high resistance. Furthermore, since a number of memory cells are connected to the word line, the stray capacitance (earth capacitance) of the word line is increased. Therefore, the word line is regarded as a CR distributed line, and the word line delay affects the access time. Similarly, the stray capacitance of the bit line is great, resulting in bit line delay. However, the bit line is generally made of aluminum, which has low resistance, so that the cause of the bit line delay differs from that of the word line delay. The bit line is charged/discharged when data is read out from the memory cell. The charge/discharge time is regarded as the bit line delay time. When a static MOS memory is used, a capacitance C of the bit line and an ON-resistance R of a MOSFET for a transfer gate of the memory cell determine the charge/discharge time. The MOSFET is formed to have minimum dimensions in favor of the integrating density and has a small mutual conductance and a high ON resistance. For example, when a 256K bit MOS SRAM is considered, 512 memory cells are used for each column. The stray capacitance of the bit line is about 4 pF. The 4-pF X (supply voltage) charge is discharged over a time interval of 20 nsec. Therefore, this delay time accounts for a large portion of the total delay time (about 50 nsec).
Power consumption of the word line in addition to the delay time thereof becomes an issue. When a given memory cell is accessed, a word line connected thereto is selected. Subsequently, one row of memory cells including the given memory cell are activated, so that the data of memory cells aligned along one row are read out to the bit lines. Thereafter, only the desired bit line is selected and data is read out therefrom through a sense amplifier. When the memory cells are energized and data signals are read out therefrom to the bit lines, power is always consumed. Therefore, when the number of memory cells connected to each word line is increased, wasteful power consumption is increased. In general, power is greatly consumed when the memory cells are energized. For example, in the case of a CMOS SRAM, 90% or more of total power consumption occurs during energization of the memory cells. High power consumption leads to heat dissipation. Therefore, the conventional memory device cannot be highly integrated in accordance with conventional memory access methods.